| dc.creator |
Tez, Serdar |
|
| dc.creator |
Unuk, Tayfun |
|
| dc.creator |
ARSLANALP, Remzi |
|
| dc.date |
2023-02-01T00:00:00Z |
|
| dc.date.accessioned |
2025-02-25T10:37:33Z |
|
| dc.date.available |
2025-02-25T10:37:33Z |
|
| dc.identifier |
bf7a8622-4926-4bdf-8975-1eaa6f91ba9b |
|
| dc.identifier |
10.1016/j.aeue.2022.154493 |
|
| dc.identifier |
https://avesis.sdu.edu.tr/publication/details/bf7a8622-4926-4bdf-8975-1eaa6f91ba9b/oai |
|
| dc.identifier.uri |
http://acikerisim.sdu.edu.tr/xmlui/handle/123456789/101204 |
|
| dc.description |
© 2022In this paper, a novel n-input 2n orthant class-AB current-mode multiplier topology is presented. The proposed analog current-mode multiplier is implemented by using two basic blocks, which are a current splitter and a one-quad multiplier. These blocks are based on the translinear circuit principle. Moreover, the designed multiplier can be easily extended for multi-input structures. Many different scenarios presenting particular usage of the proposed multiplier structure are presented as well. The functionality of all the proposed circuits utilized in different cases is verified by using the PSpice simulation program, where 0.13 μm IBM CMOS technology parameters are employed. The simulation results show that 0.225 mW power consumption and under 3 % Total Harmonic Distortion are observed for the two-input circuit. Furthermore, the bandwidth and the dynamic range of the proposed circuit for the three-input circuit are 165 MHz and 29.54 dB, respectively. |
|
| dc.language |
eng |
|
| dc.rights |
info:eu-repo/semantics/closedAccess |
|
| dc.title |
Design of Current-Mode versatile Multi-Input analog multiplier topology |
|
| dc.type |
info:eu-repo/semantics/article |
|