| dc.creator |
Aljanabi, Wissam |
|
| dc.creator |
Albayrak, Mehmet |
|
| dc.date |
2018-08-31T21:00:00Z |
|
| dc.date.accessioned |
2020-10-06T11:01:26Z |
|
| dc.date.available |
2020-10-06T11:01:26Z |
|
| dc.identifier |
b5c4b058-ffff-4306-9a2a-555a05145a53 |
|
| dc.identifier |
10.17559/tv-20170210143503 |
|
| dc.identifier |
https://avesis.sdu.edu.tr/publication/details/b5c4b058-ffff-4306-9a2a-555a05145a53/oai |
|
| dc.identifier.uri |
http://acikerisim.sdu.edu.tr/xmlui/handle/123456789/69996 |
|
| dc.description |
In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors. |
|
| dc.language |
eng |
|
| dc.rights |
info:eu-repo/semantics/openAccess |
|
| dc.title |
Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit |
|
| dc.type |
info:eu-repo/semantics/article |
|