| dc.creator |
Polat, Oevuenc |
|
| dc.creator |
Yildirim, Tuelay |
|
| dc.date |
2010-05-01T00:00:00Z |
|
| dc.date.accessioned |
2021-12-03T11:54:21Z |
|
| dc.date.available |
2021-12-03T11:54:21Z |
|
| dc.identifier |
bbafa79a-ed14-48a6-aec6-52bf98391d9d |
|
| dc.identifier |
10.1016/j.dsp.2009.10.013 |
|
| dc.identifier |
https://avesis.sdu.edu.tr/publication/details/bbafa79a-ed14-48a6-aec6-52bf98391d9d/oai |
|
| dc.identifier.uri |
http://acikerisim.sdu.edu.tr/xmlui/handle/123456789/94558 |
|
| dc.description |
This study proposes an approach to implement a General Regression Neural Network (GRNN) based on Field Programmable Gate Array (FPGA). The GRNN has a four-layer structure which is comprised of an input layer, a pattern layer, a summation layer and an output layer. The layers of GRNN are designed with fixed-point arithmetic using synthesizable VHDL (Very High Speed Integrated Circuit Hardware Description Language) code for FPGA implementation. In this work, the system was designed for pattern classification applications: however, it can be used for other application areas of GRNN. Different datasets were used to test the GRNN. Simulation results show that pattern classification by hardware implementation of GRNN has successfully achieved. The proposed system is flexible and scalable. For different classification applications, it can be modified easily according to number of inputs and number of reference data. (C) 2009 Elsevier Inc. All rights reserved. |
|
| dc.language |
eng |
|
| dc.rights |
info:eu-repo/semantics/closedAccess |
|
| dc.title |
FPGA implementation of a General Regression Neural Network: An embedded pattern classification system |
|
| dc.type |
info:eu-repo/semantics/article |
|